[james_deluca at crestnational.com: RE: [tig] HDnet]
Fri Apr 2 15:40:05 BST 2004
----- Forwarded message from James DeLuca <james_deluca at crestnational.com> -----
From: "James DeLuca" <james_deluca at crestnational.com>
Subject: RE: [tig] HDnet
To: "Rob Lingelbach" <rob at calarts.edu>
Date: Wed, 31 Mar 2004 12:36:33 -0800
and who can forget the Mirage. Or the DPE 5000, my first
"dve" unless one counts the sometimes interesting things the
Chyron 3 could do with do loops.
I was part of the Chiron III (original spelling) development
team at the then Systems Research Corp in Plainview, N.Y.
When released I was part of the first field service group to
"install" them, when not fielding calls about having to buy
"formatted" 8" diskettes from us. No microprocessors, just
a 48-bit wide (sometimes) prom-sequenced wire-wrapped
controller, using shift registers for "working" & "page"
memory and magnetic core-memory for font storage (2.5
fonts!). The display clock was an LC oscillator that was
stopped at the end of each line so the pixels would
columnize at the start of the following scan line. It was
common for customers to have to squeeze the coil to bring
adjustment within range of the trim-cap to set the osc freq.
Although the Chyron II was more capable, the 23ns resolution
was straining the 74S series logic to its limit, resulting
in innumerable hiccups when a "slow" IC caused a clock to be
missed. Then the whole screen bounced as there was no
graphical FRAME memory, only a display list that had to be
used to build the graphics in real-time.
----- End forwarded message -----
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